about chip planner in Quartus II

Thanks gee for response.

I take the picture of my test file:

1) bmp file: the chip planner design of the dely time

(http://mail.sso.ncku.edu.tw/cgi-bin/owmmbox/openwebmail-webdisk.pl/test.bmp?sessionid=l7697401*-session-0.819223314329101&currentdir=%2f&action=download&selitems=test.bmp)http://140.116.5.200/~e9493122/test.bmp (http://140.116.5.200/%7ee9493122/test.bmp)

2) jpg file: the waveform of the input/output signal in oscilloscope

(http://mail.sso.ncku.edu.tw/cgi-bin/owmmbox/openwebmail-webdisk.pl/wave.jpg?sessionid=l7697401*-session-0.819223314329101&currentdir=%2f&action=download&selitems=wave.jpg)http://140.116.5.200/~e9493122/wave.jpg (http://140.116.5.200/%7ee9493122/wave.jpg)

in this case, the fan-out connections are:

input port to the LE, which is the buffer: 2.074 ns

delay time in LE : 0.2 ns

LE to the output port : 0.612 ns

The estimate total delay time is around 3 ns, but the real total delay time is around 15 ns in scope.

You mean I should consider the input/output delay besides the delay time that are shown in chip planner.

I cannot find if the chip planner can show the input/output buffer delay as you mentioned.

Does it mean that the delay time shown on chip planner is totally not right, or I shoud add extra delay time of the input/output buffer by hand?

that is, 3 ns + (input/output delay which cannot be shown) = 15 ns

I am wondering that,

when the input/output delay is not correct, how can I trust the delay time shown in chip planner of other elements?

Thanks for your attention and help.