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Altera_Forum's avatar
Altera_Forum
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17 years ago

about chip planner in Quartus II

I tried to change the placement and routing by Chip planner, and estimate the delay time. For example, I input a signal to a buffer and then output, the delay time in Chip planner is: after I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanks gee very much.

I just followed the steps you replied.

There are surely some delay time in the input/output ports that are not shown in Chip planner.

That is a really help, thank you.

Though, the delay times in the report are still not match what I measured in scope.

If the report shown are the real delay times of my design, maybe it is wrong of my way to measure signals with the scope.