about chip planner in Quartus II

Hi,

I didnt use the Timing analysis of TimeQuest or Classic timing analyzer.

Doesn't the timing analyzer just restrict the max time of the delay, not analysize the about delay time of my design in chip planner?

Maybe I confused you, sorry.

In my design, I have to make all elements, like buffers, have the same delay time, that is why I use chip planner to arrange the logicelements.

Its OK for me if the delay times are not short, as long as they are the same.

I will check if the Timing analysizer has other functions that I didnt know.

Thanks again