about chip planner in Quartus II

Hi,

Thanks your attention, and sorry for my reply so late.

The reason why I must have the same delay time of elements is that

I am going to design the TDC(Time to Digital Convertor) by CPLD or FPGA.

The main goal is to design several stages that each one has the same delay time. After the pulse signal pass several stages and stop, say, n stages. I can have the pulse signal has time=n*(delay time of each stage).

There is a short and simple explaination.

If it is not worthy to change the placement by hand to achieve my goal.

Is there a more convenient way?

Thanks.