Forum Discussion

Tim10's avatar
Tim10
Icon for New Contributor rankNew Contributor
6 years ago

10996 Verilog HDL error at <location>: parameter "<name>" has no initial or actual value

Hi,

I'm trying to pass a parameter down a chain of modules, but I get an error in top.v about the parameter having no initial nor actual value.

Any ideas? Simple typo?

Thanks,

Tim.

testbench.v

module testbench;
 
	reg clock;
	reg in;
	wire out;
 
	top
	#(
		.WIDTH(4)
	)
	top_instantiation
	(
		.clock(clock),
		.in(in),
		.out(out)
	);
 
endmodule

top.v

module top
#(
	parameter WIDTH
)
(
	input clock,
	input in,
	output out
);
 
	bottom
	#(
		.WIDTH(WIDTH)
	)
	bottom_instantiation
	(
		.clock(clock),
		.in(in),
		.out(out)
	);
 
endmodule

bottom.v

module bottom
#(
	parameter WIDTH
)
(
	input clock,
	input in,
	output reg out
);
 
endmodule

4 Replies

  • ak6dn's avatar
    ak6dn
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    The default value of the parameter MUST be specified, it is not optional. So use: parameter WIDTH = 8 for example. You can always override it in the module instantiations.

  • Abe's avatar
    Abe
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Yes, @ak6dn is right. All parameters used within a module should be initialized with a default value. Then you can override them when creating instances. 

    module top
 #(
	parameter WIDTH = 1
 )
 (
	input   wire clock,
	input wire  [WIDTH-1:0 ]      in,
	output  reg  [WIDTH-1:0]   out
);
 
	bottom
	#(
		.WIDTH(WIDTH)
	)
	bottom_instantiation
	(
		.clock(clock),
		.in(in),
		.out(out)
	);
 
endmodule
    module bottom
#(
	parameter WIDTH = 1
)
(
	input  wire clock,
	input wire [WIDTH-1:0]  in,
	output reg [WIDTH-1:0] out   // reg is a keyword in Verilog, Do not use it as a signal/variable name.
);
 
endmodule
  • GuaBin_N_Intel's avatar
    GuaBin_N_Intel
    Icon for Contributor rankContributor
    6 years ago

    We have to follow rules defined in IEEE Standard for Verilog Hardware Description Language. For your question, that WIDTH parameter in the assignment could not be substituted correctly. You should use replication operation to make it work.

    WIDTH'd0 become {WIDTH{1'd0}}

    Here's https://en.wikipedia.org/wiki/Verilog contains some useful tutorial and example

  • Tim10's avatar
    Tim10
    Icon for New Contributor rankNew Contributor
    6 years ago

    Thanks @ak6dn​ and @Abe​ .

    Something that tripped me up is that if you synthesise the testbench (i.e. set testbench.v as the top level entity instead of top.v), then the parameter is passed down the chain even without default parameter values.

    It is possible to use a parameter in a Verilog literal? e.g. 

    my_reg <= WIDTH'd0;

    If not, where is the best place to go to request a Verilog language change and garner feedback on whether anyone would find it useful?