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Tim10's avatar
Tim10
Icon for New Contributor rankNew Contributor
7 years ago

10996 Verilog HDL error at <location>: parameter "<name>" has no initial or actual value

Hi, I'm trying to pass a parameter down a chain of modules, but I get an error in top.v about the parameter having no initial nor actual value. Any ideas? Simple typo? Thanks, Tim. testbench.v ...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Yes, @ak6dn is right. All parameters used within a module should be initialized with a default value. Then you can override them when creating instances. 

module top
 #(
	parameter WIDTH = 1
 )
 (
	input   wire clock,
	input wire  [WIDTH-1:0 ]      in,
	output  reg  [WIDTH-1:0]   out
);
 
	bottom
	#(
		.WIDTH(WIDTH)
	)
	bottom_instantiation
	(
		.clock(clock),
		.in(in),
		.out(out)
	);
 
endmodule
module bottom
#(
	parameter WIDTH = 1
)
(
	input  wire clock,
	input wire [WIDTH-1:0]  in,
	output reg [WIDTH-1:0] out   // reg is a keyword in Verilog, Do not use it as a signal/variable name.
);
 
endmodule