10996 Verilog HDL error at <location>: parameter "<name>" has no initial or actual value

Thanks @ak6dn​ and @Abe​ .

Something that tripped me up is that if you synthesise the testbench (i.e. set testbench.v as the top level entity instead of top.v), then the parameter is passed down the chain even without default parameter values.

It is possible to use a parameter in a Verilog literal? e.g.

my_reg <= WIDTH'd0;

If not, where is the best place to go to request a Verilog language change and garner feedback on whether anyone would find it useful?