Forum Discussion
Tim10
New Contributor
New Contributor10996 Verilog HDL error at <location>: parameter "<name>" has no initial or actual value
Hi, I'm trying to pass a parameter down a chain of modules, but I get an error in top.v about the parameter having no initial nor actual value. Any ideas? Simple typo? Thanks, Tim. testbench.v ...
ak6dn
Regular Contributor
Regular ContributorThe default value of the parameter MUST be specified, it is not optional. So use: parameter WIDTH = 8 for example. You can always override it in the module instantiations.
