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Tim10
New Contributor
New Contributor10996 Verilog HDL error at <location>: parameter "<name>" has no initial or actual value
Hi, I'm trying to pass a parameter down a chain of modules, but I get an error in top.v about the parameter having no initial nor actual value. Any ideas? Simple typo? Thanks, Tim. testbench.v ...
GuaBin_N_Intel
Contributor
ContributorWe have to follow rules defined in IEEE Standard for Verilog Hardware Description Language. For your question, that WIDTH parameter in the assignment could not be substituted correctly. You should use replication operation to make it work.
WIDTH'd0 become {WIDTH{1'd0}}
Here's https://en.wikipedia.org/wiki/Verilog contains some useful tutorial and example
