10996 Verilog HDL error at <location>: parameter "<name>" has no initial or actual value

We have to follow rules defined in IEEE Standard for Verilog Hardware Description Language. For your question, that WIDTH parameter in the assignment could not be substituted correctly. You should use replication operation to make it work.

WIDTH'd0 become {WIDTH{1'd0}}

Here's https://en.wikipedia.org/wiki/Verilog contains some useful tutorial and example