simultaneous access to ddrII memory by nios and vhdl entity

Hi,

If your VHDL module just provides a stream of data then you could use a DMA that pulls that data in and places it into the memory. That would just require you expose a simple streaming interface to your VHDL module which may be easier than building the master logic. Nios could then monitor the DMA to find out when it's done and safe to access the contents in the memory.

I don't think it's possible,simply because the size of bulk data is several GBs,and i don't need to send all the data ,i just need to send specific data from the bulk over the ethernet channel.The SSRAM cannot store that amount of data ,because it is limited in size (2 MB)

I have looked into UDX4 reference design.From what i see,the whole design is implemented inside the SOPC builder.Also,the vhdl entity needs to be instansciated inside the sopc builder.Let's say i did it.In nios II software , i know that i am able to access components with ease ,since the devices are memory mapped .How do i define the entity to be able to access the ddr II memory,for instance ( From definition point of view and also from vhdl code of view).Reference link/example would be welcome :)

Either you build the masters into your component or just use DMAs to move the streaming data to/from memory. What you are attempting is *very* commonly done with DMAs since it's easier to build a streaming front end then it is to create master logic. Building mastering logic is not overly difficult if you don't make it feature rich.

I have a similar problem. You say that you build a Master into your component, but what do you use for this. If I don't want a DMA, do I use the Avalon-MM Master Translator to begin with? If not, what component?

I'm referring to you (as the designer) building mastering logic into your own IP. There is no generic master block out there because it doesn't make sense to have such a thing. If there was a generic master block then you would have to tell it what address you are accessing, provide/accept data from it, and control it..... But if you are going to go through that much trouble then you might as well have the master logic integrated into your own IP otherwise you are building a lot of redundant hardware for nothing.

Right, I understand that I can map signals to the read_data, write_data, wait_request, etc, but I am concerned with how arbitration will work. I can't find any information in the Altera documentation concerning avalon arbitration. How do I handle this?

Qsys generates a round-robin arbitration scheme. You can apply weights by increasing the arbitration share on a per master-slave pairing basis (Qsys uses slave side arbitration). This is just a system setting, your master doesn't need to do anything special for this.