simultaneous access to ddrII memory by nios and vhdl entity

Qsys generates a round-robin arbitration scheme. You can apply weights by increasing the arbitration share on a per master-slave pairing basis (Qsys uses slave side arbitration). This is just a system setting, your master doesn't need to do anything special for this.

From the master perspective all you need to do is make sure you heed waitrequest. If you issue a read/write and waitrequest is asserted then your master just needs to stall until waitrequest deasserts which completes the access cycle. So it's not like a shared bus architecture where you need to worry about tri-stating your master when the arbiter kicks it out.