Forum Discussion
Altera_Forum
Honored Contributor
14 years agoIf your VHDL module just provides a stream of data then you could use a DMA that pulls that data in and places it into the memory. That would just require you expose a simple streaming interface to your VHDL module which may be easier than building the master logic. Nios could then monitor the DMA to find out when it's done and safe to access the contents in the memory.