simultaneous access to ddrII memory by nios and vhdl entity

Hi,

The easiest way is probably to create an Avalon master for your VHDL entity, either enclosing it entirely or just providing an interface from the Avalon bus to your entity outside of SOPC builder. If you then connect both your master and the NIOS processor to the memory controller in SOPC builder the Avalon bus will take care of arbitration between the two. However, it's arbitration is very fair which might not be what you want - for example, you might want your VHDL entity to have priority access over the NIOS CPU. Have a look at the multi-port front end design on the Altera website for some arbitration ideas (part of the UDX4 reference design).

Mark.