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Altera_Forum
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11 years ago

Share variables between verilog file and niosII application file(.c file)

Hello,

I am trying to do a small concept where in I have created a project on DE2-115 board. In the same project, I have also implemented niosII processor and written a simple program to toggle the LED.

In my final application that i intend to built, partly will be implemented in verilog and remaining will be implemented in .c file.

Hence there may arise a need to access (read/write) the variable through verilog file which is declared in niosII application .c file and vice-versa.

I wanted to know Is this possible and if yes how can i go about doing that.

I intend to use it in final implementation and not just for debugging.

thanks.

Jagdish

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    In HDL (i.e Verilog) you must create the variable as a register in a Memory Mapped slave.

    In Nios c code you define a pointer to the base address of the MM slave so you can access it as a regular variable.

    Remember to add 0x80000000 to the pointer address for uncached access: this prevents Nios to get the variable from cache rather than actual data possibly modified from HDL side.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Creating a reg variable is fine, I did this

    reg [31:0] SharedVar;

    But Can you kindly tell me how to define a pointer to the base address of the MM slave and,

    add 0x80000000 to the pointer address for uncached access.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I created a variable in HDL by using "reg [15:0] SharedVar;"

    But can you please tell me how to define a pointer to the base address of the MM slave and

    how to add 0x80000000 to the pointer address for uncached access

    thanks
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I went through the template details and i have a question. Do i need to do to all this access the shared variables. Can you kindly suggest me any other method by which i can access the same memory location of onchip memory or SDRAM using HDL and C code.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    The template implements far more than you need. For example it defines 16 registers (= shared variables) whereas you only need one; moreover it manages different data access modes, variable data width and many other features.

    If you don't bother keeping all this stuff in your code, you can integrate it straight in your code. Otherwise cut away the non essential bells and whistles.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    my apologies for replying this late.

    before trying the template wanted to get some clarity.

    Is the above template applicable even while using On-chip memory? OR

    Is it that on-chip memory can be handled in much simpler way and directly using hdl and niosII?

    One more question where are the variables stored that are declared in hdl. (integer, reg). can't this variable's memory location be accessed using niosII.

    thanks

    -Jagdish
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Is the above template applicable even while using On-chip memory? OR

    Is it that on-chip memory can be handled in much simpler way and directly using hdl and niosII?

    --- Quote End ---

    The above template DOES apply to onchip memory.

    --- Quote Start ---

    One more question where are the variables stored that are declared in hdl. (integer, reg). can't this variable's memory location be accessed using niosII.

    --- Quote End ---

    That's exactly the purpose of the MM slave. It maps the hdl registers to Nios address space
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Sorry, I have one doubt over here,

    Implementing MM slave will allow me to share maximum 16 regs of HDL. What if i want to fill 10Mbytes of SDRAM location in HDL and later on use it in NiosII application?

    Will the MM slave still be the answer to this.

    I doubt this because in MM slave i found only 16 regs were available.

    In my application, I want to fill the video data (Around 10Mbytes) in SDRAM using HDL and later on retrieve the Data from SDRAM in niosII application for sending it to external world.

    -Jagdish
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    That's only a template and 16 regs are defined as typical example.

    You could even have defined a single register or, on the other hand, extend the address range to whatever you need.

    In a generic case where you have:

    reg [31:0] ram[DEPTH-1:0];

    You access from Avalon MM slde something like this: 

    
always @(posedge clk) begin
    if(slave_write)  
          ram  <= slave_writedata;
    else if  (slave_read)
          slave_readdata  <= ram;
end