Share variables between verilog file and niosII application file(.c file)

In HDL (i.e Verilog) you must create the variable as a register in a Memory Mapped slave.

In Nios c code you define a pointer to the base address of the MM slave so you can access it as a regular variable.

Remember to add 0x80000000 to the pointer address for uncached access: this prevents Nios to get the variable from cache rather than actual data possibly modified from HDL side.