Share variables between verilog file and niosII application file(.c file)

That's only a template and 16 regs are defined as typical example.

You could even have defined a single register or, on the other hand, extend the address range to whatever you need.

In a generic case where you have:

reg [31:0] ram[DEPTH-1:0];

You access from Avalon MM slde something like this:

always @(posedge clk) begin
    if(slave_write)  
          ram  <= slave_writedata;
    else if  (slave_read)
          slave_readdata  <= ram;
end