Sdram access in HDL and Nios II

You need to add an Avalon MM master interface to your custom component.

Thanks for your reply.

You don't have to worry about simultaneous accesses but you do have to worry about cache coherency and data hazards. If your hardware needs to access blocks of memory at a time then I recommend using a DMA engine to move the data to/from memory and your accelerator so that you don't have to implement it yourself.

Thank you. Data coherency is indeed important for my application. The C++ application on Nios II serves as a slideshow player for text and images. Everytime a new frame needs to be displayed it pushes this pixel data (48 x 112 pixels of 8 bits) to the sdram memory. The custom ip core I will write should than display this data on an electronic sign using the GPIO port.

If you only have 48x112 bytes of image data, it is probably easier to use dual-ported on-chip memory inside the vhdl component and write directly to it from your C code. That way you only have to write the simpler Avalon slave interface.

That's interesting. Could you maybe tell me more about how I can do this?

I hope I understood this correctly:

You create a component that has the on-chip memory inside it (not the on-chip component that appears in SOPC Builder). If you want a verilog example shoot me PM with your email address and I can send you something I'm working on that does this.

i have made avalon master components and my own DMA access to an offchip SDRAM using my avalon master and an SDRAM controller. Its not very hard especially if you are just doing writes and no reads. Reads take a little bit more work.

Ok, thanks again for the replies. I think this evening I'll try the custom dual port memory approach and keep the sdram approach as a backup :rolleyes: