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Altera_Forum
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15 years ago

Sdram access in HDL and Nios II

Hi I'm fairly new to FPGA programming. I would like to use the onboard sdram memory of my DE2-70 board to pass data between c++ software, running on a Nios II cpu and a verilog component. W...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thank you. Data coherency is indeed important for my application. The C++ application on Nios II serves as a slideshow player for text and images. Everytime a new frame needs to be displayed it pushes this pixel data (48 x 112 pixels of 8 bits) to the sdram memory. The custom ip core I will write should than display this data on an electronic sign using the GPIO port.

Maybe I'm a little naïve but couldn't I just reserve 1 bit to indicate a new frame has to be displayed? This bit could be set to 1 by the c++ application and to 0 by the ip core (when the frame has been written).