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Altera_Forum
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15 years ago

Sdram access in HDL and Nios II

Hi I'm fairly new to FPGA programming. I would like to use the onboard sdram memory of my DE2-70 board to pass data between c++ software, running on a Nios II cpu and a verilog component. W...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for your reply.

In that case, would I need to change the way I access the sdram memory in c++. Or can I just keep directly addressing the base pointer?

And can I read/write to the sdram memory from both locations (nios and custom ip core) without worrying about collisions or data corruption during simultaneous operations?

Thanks