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Altera_Forum
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15 years ago

Sdram access in HDL and Nios II

Hi I'm fairly new to FPGA programming. I would like to use the onboard sdram memory of my DE2-70 board to pass data between c++ software, running on a Nios II cpu and a verilog component. W...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I hope I understood this correctly:

I can define a dual port memory core (like in the file I attached) and add an Avalon slave to one of the two ports?

Through this Avalon slave I can than access the memory from within the Nios II?

Trough the second port I can also access the memory from within my custom IP core?

Is this correct? What I don't understand is how I can add the ram core to the SOPC system and still connect to the other available port from another custom ip core. I'll just get started and see where it takes me.