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Altera_Forum's avatar
Altera_Forum
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15 years ago

Sdram access in HDL and Nios II

Hi I'm fairly new to FPGA programming. I would like to use the onboard sdram memory of my DE2-70 board to pass data between c++ software, running on a Nios II cpu and a verilog component. W...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You don't have to worry about simultaneous accesses but you do have to worry about cache coherency and data hazards. If your hardware needs to access blocks of memory at a time then I recommend using a DMA engine to move the data to/from memory and your accelerator so that you don't have to implement it yourself.

More details about what you are attempting to do in hardware will probably result in a less generic answer.