Required Nios components

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I have set the ddr controller to run at half rate (125MHz/2=62.5MHz), doubled the burst and now Nios runs fine, no need of pipeline bridge.

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you can put your cpu and other peripherial (jtag pio etc) to work on 62.5 and your ddr2 to work on 125 (normally using clock crossing without pipeline).

if your cpu will work with clock over 65 mhz you NEED to put pipeline bridge........and peripherial does not work fine with high values of clocks..... is better you put cpu and ram to work with clocks over peripherials clock....

try it..........

cheers

Franz Wagner

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In my experience it is difficult to make the NIOS CPU run over 100MHz without a pipeline bridge before the JTAG debug module.

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Hmmmmm... This is interesting to me. I have been having trouble getting text to display correctly on the Nios II Console using prntf() statements. A little text like "Hello World" display fine, but add more text and it stutters terribly. I've been thinking that it is probably due to JTAG UART timing somehow, but other features like SignalTap that us JTAG seem to work fine.

Could you describe how to insert a pipeline bridge in the JTAG Debug module interface? Maybe this would solve my problem.

Thanks in advance, I've learned a lot from your posts.

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and dont forget conect the data slave and data master..........

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I'm not sure I understand. Do I use one pipeline_bridge and connect its s0 to both the cpu data_master and instruction_master, then connect the pipeline_bridge m0 to the jtag_debug_module?

Or... Should I use two pipe_line bridge instances - one for the data_master and one for the instruction_master?

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I'm not sure I understand. Do I use one pipeline_bridge and connect its s0 to both the cpu data_master and instruction_master, then connect the pipeline_bridge m0 to the jtag_debug_module?

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yes only one for data and instruction.......but i agree with Daixiwen ..I'm not sure your problem is related to that

if you rise frequence of cpu dont rise the frequence of jtag ......keep jtag uart with same frequence with it works and rise only cpu frequence ...

use a clock crossing bridge to do that.........

good luck ..

Franz Wagner

Thanks for all the great suggestions.

I constrained the design and ran a timing analysis which is fine. I changed the JTAG UART clock to 5 MHZ with the Nios II CPU running at 50 MHZ and a clock crossing bridge between them.

I also tried a pipeline bridge in series with the JTAG UART.

None of this made any change whatsoever to the corrupted text I'm getting on the Nios II Console.

I tested a similar Qsys design on the Altera Cyclone III Nios II NEEK and it runs fine - uh oh, something must be wrong with my board!!!

Here's the text I get on the NEEK:

<----> Nios II Memory Test. <---->

This software example tests the memory in your system to assure it

is working properly. This test is destructive to the contents of

the memory it tests. Assure the memory being tested does not contain

the executable or data sections of this code or the exception address

of the system.

And this is what I get on my board running the same Memory Test app:

<<---- iissII eeooyyTTss.. <<---->

hhssssffwwrr xxmmll eett hh eeooyyii oorrssssee ooaassrr ttii ookknn rrpprryy TTii eettii eettuuttvv ootteeccnneett fftteemmmmrr ttttssss ssuueetteemmmmrr eenn eettddddee oo oottii

the executable or data sections of this code or the exception addres

fftteessssee..

Do you have enough memory in your design? A collision between heap and stack could lead to something like this.

Anyway if Timequest says the timing requirements are met then pipeline bridges won't change anything. I wonder if 5MHz isn't too low for the JTAG uart though.

My external SRAM is 516K by 16 bits, so I should be ok on size, right? I keep wondering about things like ground bounce, bad address and/or data lines, etc. as the memory chip is on an add-on daughter card. I've tested the memory with a straight hardware solution that did not involve Nios II or even Qsys. I've also tested it with System Console using a tcl script to exercise the SRAM. Also, when running a Nios II app the elf file always loads and verifies with no problem.

The corrupted text is always the same. I would think that a timing issue would yield variable results.

I've shifted the address lines and got exactly the same results. I may try shuffling the data lines to see what that does.

The 5 MHz JTAG UART was just a temporary test. Otherwise I have been running the entire system at 50 MHz. I do notice that if I crank up the system clock to 100 MHz it has trouble reading the System ID and Timestamp.