Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Required Nios components

Hello, I am trying to develop a very simple Nios cpu to run Hello world application. I have created a design: http://i55.tinypic.com/a29isy.jpg As You can see, I have inserted DDR2 memory ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

and dont forget conect the data slave and data master..........

--- Quote End ---

I'm not sure I understand. Do I use one pipeline_bridge and connect its s0 to both the cpu data_master and instruction_master, then connect the pipeline_bridge m0 to the jtag_debug_module?

Or... Should I use two pipe_line bridge instances - one for the data_master and one for the instruction_master?