Required Nios components

Thanks for all the great suggestions.

I constrained the design and ran a timing analysis which is fine. I changed the JTAG UART clock to 5 MHZ with the Nios II CPU running at 50 MHZ and a clock crossing bridge between them.

I also tried a pipeline bridge in series with the JTAG UART.

None of this made any change whatsoever to the corrupted text I'm getting on the Nios II Console.

I tested a similar Qsys design on the Altera Cyclone III Nios II NEEK and it runs fine - uh oh, something must be wrong with my board!!!

Here's the text I get on the NEEK:

<----> Nios II Memory Test. <---->

This software example tests the memory in your system to assure it

is working properly. This test is destructive to the contents of

the memory it tests. Assure the memory being tested does not contain

the executable or data sections of this code or the exception address

of the system.

And this is what I get on my board running the same Memory Test app:

<<---- iissII eeooyyTTss.. <<---->

hhssssffwwrr xxmmll eett hh eeooyyii oorrssssee ooaassrr ttii ookknn rrpprryy TTii eettii eettuuttvv ootteeccnneett fftteemmmmrr ttttssss ssuueetteemmmmrr eenn eettddddee oo oottii

the executable or data sections of this code or the exception addres

fftteessssee..