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I'm not sure I understand. Do I use one pipeline_bridge and connect its s0 to both the cpu data_master and instruction_master, then connect the pipeline_bridge m0 to the jtag_debug_module?
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yes only one for data and instruction.......but i agree with Daixiwen ..I'm not sure your problem is related to that
if you rise frequence of cpu dont rise the frequence of jtag ......keep jtag uart with same frequence with it works and rise only cpu frequence ...
use a clock crossing bridge to do that.........
good luck ..
Franz Wagner
Honored Contributor
