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Altera_Forum
Honored Contributor
Honored ContributorRequired Nios components
Hello, I am trying to develop a very simple Nios cpu to run Hello world application. I have created a design: http://i55.tinypic.com/a29isy.jpg As You can see, I have inserted DDR2 memory ...
Altera_ForumHonored Contributor
Honored ContributorDo you have enough memory in your design? A collision between heap and stack could lead to something like this.
Anyway if Timequest says the timing requirements are met then pipeline bridges won't change anything. I wonder if 5MHz isn't too low for the JTAG uart though.
