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Paul83's avatar
Paul83
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2 years ago

read/ write with IORD_32DIRECT and IOWD_32DIRECT problem

Hi All,

I am using the quartus pro 23.4 with Asling 23.4.1
I have used the avalon_slave bus in my own module. After building the BSP and I try to run the IORD_32DIRECT (base_address) or even IOWD_32DIRECT(base_address, data)
and I found there are 8 read/ write pulse when I use the signal tap analyser to check on it.

See anyone have idea on this issue. Thank you very much.

Best regards,

Paul

Embedded Applications Layer
Nios Architecture
Nios Cpu

9 Replies

  • symmt_Intel's avatar
    symmt_Intel
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    2 years ago

    Hi Paul,

    Just to confirm, are you using Nios V?

    Could you go into more details, for example PD system?

    Best regards,

    Sho

    • Paul83's avatar
      Paul83
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      2 years ago

      Hi Sho,

      Thanks for your reply and I am using the Nios V and below is the Nios V and the corresponding Avalon_ext_bus_32x64k module with the port information in the previous post.

      Best regards,

      Paul

      • Paul83's avatar
        Paul83
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        2 years ago

        Hi Sho,

        I try to make the thing simple. The connection my own module avalon_timeout2 to the Nios V CPU in the platform design as show in the pic (PD.png)
        For the avalon_timeout2 is used to access the memory in below VHDL code (sorry that please ignore the name of the module "timeout", as I just quickly modify it)

        Then, in the Ashling IDE, I just try to write and read the memory. However, the output are also abnormal by this simple try.


        IOWR_32DIRECT(AVALON_TIMEOUT2_0_BASE,0x0,0x00000001); //write address 0 with data 1
        uint rddata = IORD_32DIRECT(AVALON_TIMEOUT2_0_BASE,0x0); //read address 0

        IOWR_32DIRECT(AVALON_TIMEOUT2_0_BASE,0x4,0x00000004); //write address 0x04 with data 0x04
        rddata = IORD_32DIRECT(AVALON_TIMEOUT2_0_BASE,0x4); //read address 0x04

        when I run the 1st IOWR_32DIRECT(AVALON_TIMEOUT2_0_BASE,0x0,0x00000001), it seem the read pulse is triggered, address is changing.... (waveform.png)
        when I run others 3 code. There are no trigger in the signal tap analyser. It make me confuse....

        Do you have any idea on this ?

        Thanks

        Paul

        The VHDL code for avalong_timeout2

        avalon_timeout2 :
        Library IEEE;
        use IEEE.std_logic_1164.all;
        use IEEE.numeric_std.all;
        entity AVALON_TIMEOUT2 is
        port(
        -- Clock/Reset interface
        clk : in std_logic;
        reset : in std_logic; -- an active high reset signal
        -- IO interface for read / write access
        write : in std_logic;
        read : in std_logic;
        address : in std_logic_vector (15 downto 0); -- with 2 address
        writedata : in std_logic_vector(31 downto 0);
        readdata : out std_logic_vector(31 downto 0)
        );
        end AVALON_TIMEOUT2;
        architecture RTL of AVALON_TIMEOUT2 is
        type memory_array is array (0 to 65535) of std_logic_vector (31 downto 0);
        signal memory : memory_array := (others => (others =>'0'));
        signal read_data : std_logic_vector(31 downto 0);
        begin
        CONTROL : process(reset, clk)
        begin
        if reset = '1' then
        read_data <= (others => '0'); -- reset read_data
        elsif Rising_Edge(clk) then
        if write = '1' then
        memory(to_integer(unsigned(address))) <= writedata;
        end if;
        if read = '1' then
        read_data <= memory(to_integer(unsigned(address)));
        end if;
        end if;
        readdata <= read_data;
        end process CONTROL;
  • symmt_Intel's avatar
    symmt_Intel
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    2 years ago

    Hi Paul,


    Looking at the VHDL code, it seems to me that there is no part which ​causes such errors.

    Could you check if the memory address you access is correct?

    What are the address of the memory you want to r&w (configured on Platfor Designer), and AVALON_TIMEOUT2_0_BASE?


    Best regards,

    Sho Yamamoto


  • Paul83's avatar
    Paul83
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    2 years ago

    Hi Sho,

    Thanks for your response.

    In the platform design the base address from 0x00100000 to 0x0013ffff for the 16bit address on the avalon bus.

    This time the abnormal is different. When I use the IOWR_32DIREC function, the read pulse is appear. It is very strange.

    However, I try to change the address bus width to 12 bit, the base address 0x00058000 to 0x0005bfff. The signal capture from signal tap analyzer become normal.

    Best Regards,

    Paul

  • symmt_Intel's avatar
    symmt_Intel
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    2 years ago

    Hi Paul,


    You mean you can now see correct waveform on signal tap by changing address bit width?


    Best regards,

    Sho Yamamoto


  • Paul83's avatar
    Paul83
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi Sho,

    yes, If I try to change the address bus to 12 bit in my custom module. Then, it work properly.
    However, it need 16bit address in my module in my application.

    Best regards,

    Paul

  • symmt_Intel's avatar
    symmt_Intel
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    2 years ago

    Hi Paul,


    Could you confirm the following?

    1. Please decrease the clock to for example 50MHz and run? I'm wondering if the design meets the timing.
    2. What is the frequency of JTAG? Please see if decreasing it to 6MHz works.
    3. What is the target memory you are trying to access? Is it a custom memory?


    Best regards,

    Sho Yamamoto


    • Paul83's avatar
      Paul83
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      2 years ago

      Hi Sho,

      Thanks of your reply. According to your suggestion

      1. Please decrease the clock to for example 50MHz and run? I'm wondering if the design meets the timing.

      Try to decrease the clock with lower frequency e.g it give the same situation.

      1. What is the frequency of JTAG? Please see if decreasing it to 6MHz works.

      Yes, I tried to use the lower clock rate on JTAG with 6MHz, it also give the same situation.

      1. What is the target memory you are trying to access? Is it a custom memory?

      My target is to access the custom module (custom made interface with 16bit address bus - as there are different register or memory in this interface)

      I am look on the Nios V cache memory. It seems that it use 32bytes (8 words) per cache line. Don't know it is related to the cache memory to give multiple read/write pulse.

      Thanks

      Best regards,

      Paul