Forum Discussion
symmt_Intel
New Contributor
2 years agoHi Paul,
Looking at the VHDL code, it seems to me that there is no part which causes such errors.
Could you check if the memory address you access is correct?
What are the address of the memory you want to r&w (configured on Platfor Designer), and AVALON_TIMEOUT2_0_BASE?
Best regards,
Sho Yamamoto