read/ write with IORD_32DIRECT and IOWD_32DIRECT problem

Hi Sho,

Thanks of your reply. According to your suggestion

1. Please decrease the clock to for example 50MHz and run? I'm wondering if the design meets the timing.

Try to decrease the clock with lower frequency e.g it give the same situation.

1. What is the frequency of JTAG? Please see if decreasing it to 6MHz works.

Yes, I tried to use the lower clock rate on JTAG with 6MHz, it also give the same situation.

1. What is the target memory you are trying to access? Is it a custom memory?

My target is to access the custom module (custom made interface with 16bit address bus - as there are different register or memory in this interface)

I am look on the Nios V cache memory. It seems that it use 32bytes (8 words) per cache line. Don't know it is related to the cache memory to give multiple read/write pulse.

Thanks

Best regards,

Paul