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Altera_Forum
Honored Contributor
20 years agoPCI in uClinux
Does suported PCI in uClinux for NIOS II with Altera PCI Compiler 4.0 pci_mt_32 megafuntion ?
Anywho uses this options ? I can't compile kernel with PCI support... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif Thnx...21 Replies
- Altera_Forum
Honored Contributor
--- Quote Start --- originally posted by hippo@Sep 25 2006, 11:48 PM it looks like that the chip does not repsonse to memory acces.so the access timeout.
please use scope or la, to look at pci bus lines, frame, irdy, trdy , ad[].
within a short pci memory registers access loop.
check the altera pci core config page 4.
try config the e1000 to a lower memory address in pci mmemory space,
and check the memory access.
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--- Quote End --- If you do not have access to a LA or don't want to connect a lot of wire (a bit boring http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/dry.gif ), a good choice is to use SignalTap II Logic Analyzer which is included with Quartus. You will have to recompile your design, and of course SignalTap II IP will need some extra LE. You must also have a full Quartus license in order to use SignalTap II, or with the Quartus Web Edition you must enable 'Talkback feature', althought I'm not sure. Hope this will help. Regards.
- Altera_Forum
Honored Contributor
Hi Hippo, Hi Bigboss
Thanx for your answers... i have now logged the PCI Bus DATA-READ (BE = 0x06h). Here is a plot from the SignalTap trace: trace-picture (http://www.mabcom.de/pci.jpg) Maybe something wrong? My Software gives a 0x32bfffff when read from Adress 0x200000. In the Signaltap you see another value. Why? Any ideas? What about the PCI clk? I have clocked the Signaltap Analyser with PCI_CLK. I generate a 33MHz CLK and give it to CLK_PCI_COMPILER input clk and also the same clock to the Hardware PCI_CLK_Pin. I have also added Phase-Shifting, but that doesn't work. I hope you can help me http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif Bye Marco - Altera_Forum
Honored Contributor
Hi Marco,
There are no active devsel nor trdy. So the e1000 is not responding to memory access. The ad bus is floating, and the value is meaningless. Can you give your sopc ptf and altpci.c ? I will check the translation table. The PCI clock might be OK, since you can access the config space. - Altera_Forum
Honored Contributor
Hi Hippo,
The System PTF File you can find here (http://www.mabcom.de/std_2s60.ptf) The altpci.c-File you can find here (http://www.mabcom.de/altpci.c) I hope you can find anything http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif Thanx Marco --- Quote Start --- originally posted by hippo@Sep 26 2006, 11:24 PM hi marco,there are no active devsel nor trdy.
so the e1000 is not responding to memory access.
the ad bus is floating, and the value is meaningless.
can you give your sopc ptf and altpci.c ?
i will check the translation table.
the pci clock might be ok, since you can access the config space.
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- Altera_Forum
Honored Contributor
I Have found out another funny thing.
The Altera PCI Bridge has PCI-Bus Access at 0x060000000. On Page 4 from Setup Offset 0x0000000 is Config, 0x00100000 is Mem and so on. So, when the System accesses the PCI-Bus it writes a 0x86100000 for Mem in the PCI-Bar, but the physical Bus Access is to Address 0x100000. So the PCI-Device doesn't answer. It's not the same address. I have patched the Linux kernel to mask out the highest bit. And i have told the PCI-Bridge-Setup to map the Mem to 0x061000000. Now the access is ok. I can read the Config-Register with Memory Access. But when the Ethernet-Driover wants to access the device it doesn't work. Please see here a Memory Access Trace: mem_trace (http://www.mabcom.de/memtrace1.jpg) As you see, the DEVSEL goies Low, also the TRDY, but why so late? Does the Master abort the transfer? And why are there hundreds off accesses to the same Address? Thanx Marco - Altera_Forum
Honored Contributor
Hi Marco,
When I perpared the altpci driver, I had tried to simplify the address translation between pci space and avalon space. I decided to use the same address mapping for both spaces, so that I don't have to add another address tables in drivers. I checked your ptf and altpci.c . Please update in the pci core toolbench, page 4, avalon config. change the pci base address in the address translation table, row 0, pci config space, pci base 0, == avalon 0x06000000 uncached to nios2 0x86000000 row 1, pci mem space, pci base 0x86100000, == nios2 0x86100000 row 2, pci mem space, pci base 0x86200000, == nios2 0x86200000 .... row 7, pci io space, pci base 0x86700000, == nios2 0x86700000 Note, we need to uncache the access for nios2, by setting address bit 31 . Hope this will help. Hippo - Altera_Forum
Honored Contributor
Hi Hippo,
PCI problems solved. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif GigaBit Ethernet works fine with uClinux http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif But your last tip doesn't work. The PCI-Compiler doesn't accept the highest Bit set. To get PCI for me to work i just masked out the highest bit in the Device Bar Setup in ALTPCI.C I wondered why you haven't done it. I think PCI can't work without that. Or just I/O-Access is possible. Solong, i have a cheap and well working Gigabit-Ethernet on my uClinux-Board. Tomorrow i will make a performance test. The results i will post here. Thanx and Bye Marco --- Quote Start --- originally posted by hippo@Sep 27 2006, 11:33 PM hi marco,when i perpared the altpci driver, i had tried to simplify the address translation between pci space and avalon space. i decided to use the same address mapping for both spaces, so that i don't have to add another address tables in drivers.
i checked your ptf and altpci.c .
please update in the pci core toolbench, page 4, avalon config.
change the pci base address in the address translation table,
row 0, pci config space, pci base 0, == avalon 0x06000000 uncached to nios2 0x86000000
row 1, pci mem space, pci base 0x86100000, == nios2 0x86100000
row 2, pci mem space, pci base 0x86200000, == nios2 0x86200000
....
row 7, pci io space, pci base 0x86700000, == nios2 0x86700000
note, we need to uncache the access for nios2, by setting address bit 31 .
hope this will help.
hippo
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- Altera_Forum
Honored Contributor
Hi Hippo,
how fast is the PCI implementation? Does it works with DMA? I think it's a little bit slowly when i test the PCI Performance with Giga-Ethernet. I think the Linux TCP-IP-Stack doesn't use the PCI-Memory Access. Can we solve it quickly? Thanx Marco - Altera_Forum
Honored Contributor
--- Quote Start --- originally posted by mabcom@Sep 29 2006, 01:45 AM hi hippo,how fast is the pci implementation?
does it works with dma? i think it's a little bit slowly when i test the pci performance with giga-ethernet.
i think the linux tcp-ip-stack doesn't use the pci-memory access.
can we solve it quickly?
thanx
marco
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--- Quote End --- Hi MadCom, would it be possible for you to create on "how-to" on Nios Wiki, explaining what you did (hardware, Ip cores used... and of course uClinux driver). I think it would help a lot of people. Thanx. Regards.
- Altera_Forum
Honored Contributor
Hi,
i have now tested a little bit. To Hippo: DMA works. The PCI accesses the SDRAM via Master-Access. The maximum speed i reached with a Nios/f @100MHz, and CAS2/SDRAM@100MHz is: 47Mbit/s for TCP and 49Mbit/s for UDP. I think the Nios is not able to give more.... These are values under uClinux. Therefore the are not too bad, i think. But the best thing is, that PCI works. So really everything can be combined with uClinux (Wlan, MiniPCI, SCSI and so on...) To Bigboss25: I will write a NiosWiki Article soon about that. Solong Marco --- Quote Start --- originally posted by bigboss25+sep 29 2006, 02:15 am--><div class='quotetop'>quote (bigboss25 @ sep 29 2006, 02:15 am)</div>--- quote start ---
<!--quotebegin-mabcom@Sep 29 2006, 01:45 AM hi hippo,
how fast is the pci implementation?
does it works with dma? i think it's a little bit slowly when i test the pci performance with giga-ethernet.
i think the linux tcp-ip-stack doesn't use the pci-memory access.
can we solve it quickly?
thanx
marco
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18494)
--- quote end ---
--- Quote End --- Hi MadCom, would it be possible for you to create on "how-to" on Nios Wiki, explaining what you did (hardware, Ip cores used... and of course uClinux driver). I think it would help a lot of people. Thanx. Regards. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18495)</div> [/b] --- Quote End ---