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originally posted by hippo@Sep 25 2006, 11:48 PM
it looks like that the chip does not repsonse to memory acces.
so the access timeout.
please use scope or la, to look at pci bus lines, frame, irdy, trdy , ad[].
within a short pci memory registers access loop.
check the altera pci core config page 4.
try config the e1000 to a lower memory address in pci mmemory space,
and check the memory access.
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If you do not have access to a LA or don't want to connect a lot of wire (a bit boring
http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/dry.gif ), a good choice is to use SignalTap II Logic Analyzer which is included with Quartus. You will have to recompile your design, and of course SignalTap II IP will need some extra LE.
You must also have a full Quartus license in order to use SignalTap II, or with the Quartus Web Edition you must enable 'Talkback feature', althought I'm not sure.
Hope this will help.
Regards.