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Altera_Forum
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19 years ago

Parallel Flash Problems

I have searched tediously through the forums for any help on this, and have tried a lot of different things.

I am using the same Flash chip as on the NIOS II Cyclone II Eval board on a custom design; the AM29LV128REI (16-bit design in 8-bit mode). When I run nios2-flash-programmer --debug, it reads the CFI table, however, only a few bytes are a wrong, and it always seems to be the same bytes. I tried extending the timings to make them longer, and this changes the results, but it's still not correct. Sometimes, when it reads it correct, I can't program it, I get verify errors.

I have used SignalTap to try and see what's going on, and it hasn't helped narrow down the problem. For example, when reading one of hte bytes from the CFI table, the address gets setup correctly, CEn goes low, then OEn a few cycles later. Sometimes, this doesn't produce the proper value; instead, the value shows up on the next cycle (address+1). On a 16-bit device in x8 mode, the reading of address and address+1 should be the same value. Since the software probably latches data in on the first reading, it is sometimes wrong.

Anyway, it's hard to picture this being a signal-integrity problem since it's such low speed, and it's not even that far away. Any hints on debugging this?

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    You can try download a program into dram, and try out flash read write from dram. So that you can isolate if it is a jtag problem or others.

    You can try to set io pin current stength to minimum. The jtag singal is weak. You should also try add series terminator / pull high to jtag signals.
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    --- Quote Start ---

    originally posted by jdhar@Feb 22 2006, 07:27 PM

    on a 16-bit device in x8 mode, the reading of address and address+1 should be the same value.

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12894)

    --- quote end ---

    --- Quote End ---

    I do not use AM29LV128M,

    but

    I think, that&#39;s not correct, because in BYTE mode A0 should be connected to

    (D15-A-1) of the flash (see Texas_rev01_sch_production.pdf in

    ..\documents\nios_cycloneII_2c35 of nios 5.1

    best regards
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    --- Quote Start ---

    originally posted by hippo@Feb 22 2006, 08:35 PM

    you can try download a program into dram, and try out flash read write from dram. so that you can isolate if it is a jtag problem or others.

    you can try to set io pin current stength to minimum. the jtag singal is weak. you should also try add series terminator / pull high to jtag signals.

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12896)

    --- quote end ---

    --- Quote End ---

    Hey hippo; I don&#39;t see how setting the current strength to minimum will help JTAG? I can&#39;t set the signal strengths on the JTAG pins (I don&#39;t think). And I don&#39;t think JTAG is the problem since I Can download code and run from DRAM without problem, as well as use Signal Tap. Also, I have tried what you said, reading/writing Flash from DRAM, and similar errors happen; I can confirm that errors I see with SignalTap are the same errors detected in code.

    I have also replaced the chip, so it&#39;s not the chip... and the circuit is a duplicate of what is on the Cyclone II dev board (just for some more info)
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    --- Quote Start ---

    originally posted by fischer+feb 22 2006, 08:47 pm--><div class='quotetop'>quote (fischer @ feb 22 2006, 08:47 pm)</div>

    --- quote start ---

    <!--quotebegin-jdhar@Feb 22 2006, 07:27 PM

    on a 16-bit device in x8 mode, the reading of address and address+1 should be the same value.

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12894)

    --- quote end ---

    --- Quote End ---

    I do not use AM29LV128M,

    but

    I think, that&#39;s not correct, because in BYTE mode A0 should be connected to

    (D15-A-1) of the flash (see Texas_rev01_sch_production.pdf in

    ..\documents\nios_cycloneII_2c35 of nios 5.1

    best regards

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12897)</div>

    [/b]

    --- Quote End ---

    I can&#39;t tell what you mean exactly by your post; but I have the D15 pin as A0, and then A0 on the Flash is really A1, A1 is A2 etc... I think I forgot to mention it, but the addresses are doubled. So if in the datasheet, a CFI table parameter is at address 0x20, this is word address 0x20, but the value is only a byte wide. So in x8 mode, you have to read from address 0x40 (this is taking into account teh shift of address lines).. but 0x41 will read the same value again. If you want to read word at 0x21 in x16, you need to read byte 0x42.

    I hope that wasn&#39;t too confusing.. it&#39;s hard to put into words. As I mentioned, the circuit is a duplicate of the Cyclone II dev board, and they have A0 connected to the DQ15 pin.
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    For current strength, I meant flash io pins. Lower current stength will lower slew, and lower noise.

    Try running a read/write flash loop from dram, and hook up scope to check the addr/data/cmd waveform.

    Did you use uncached access?
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    I put the signal strength as minimum... I attached a waveform of the problem.

    This waveform shows read accesses of address 0x58 -> 0x5B. The data byte I&#39;m interested in is 0x5A and 0x5B. As you can see, while FL_OEn is asserted for 0x5A, the data is going crazy... and then at 0x5B, it&#39;s ok. For some reason, the word before that is ok... 0xFF is the correct value for 0x5A and 0x5B.

    signaltap image (http://www.fps-tech.net/images/st.jpg)

    The code I am using to generate this is:

    /* Reset */

    IOWR_8DIRECT(0,0,0xF0);

    /* Put into CFI Mode */

    IOWR_8DIRECT(0,0xaa,0x98);

    /* Read IDs */

    printf("0x%X 0x%X 0x%X 0x%X\n",IORD_8DIRECT(0,0x5a),IORD_8DIRECT(0,0x5b),IORD_8DIRECT(0,0x5c),IORD_8DIREC

    T(0,0x5d));

    printf("0x%X 0x%X 0x%X 0x%X\n",IORD_8DIRECT(0,0x5e),IORD_8DIRECT(0,0x5f),IORD_8DIRECT(0,0x60),IORD_8DIREC

    T(0,0x61));

    The base address is 0x0 for the Flash...
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    If it is not logic problem, then it must be board wiring problem. Try some walking tests on the addr/data, with different set of data pattern. make sure you have proper control signal such as reset# etc.

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Hi,

    Do you use pull up resistors with CE#, OE#, WE#, RST# and use pull down resistor with BYTE#?

    I think you should check schematics first to confirm nothing wrong and solder rightly.

    Regards,

    LiangYi
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    --- Quote Start ---

    originally posted by liangyi@Feb 23 2006, 01:23 AM

    hi,

    do you use pull up resistors with ce#, oe#, we#, rst# and use pull down resistor with byte#?

    i think you should check schematics first to confirm nothing wrong and solder rightly.

    regards,

    liangyi

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12907)

    --- quote end ---

    --- Quote End ---

    Yes, they are all pulled up and down. I don&#39;t know how to post attachments, so I put the PDF of the schematic here:

    http://www.fps-tech.net/docs/flash.pdf (http://www.fps-tech.net/docs/flash.pdf)
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Hi,

    I look the flash schematic, nothing wrong.

    Have you checked the flash soldering?

    Does flash pins have short circuit?