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Altera_Forum
Honored Contributor
20 years agoParallel Flash Problems
I have searched tediously through the forums for any help on this, and have tried a lot of different things. I am using the same Flash chip as on the NIOS II Cyclone II Eval board on a custom d...
Altera_Forum
Honored Contributor
20 years agoI put the signal strength as minimum... I attached a waveform of the problem.
This waveform shows read accesses of address 0x58 -> 0x5B. The data byte I'm interested in is 0x5A and 0x5B. As you can see, while FL_OEn is asserted for 0x5A, the data is going crazy... and then at 0x5B, it's ok. For some reason, the word before that is ok... 0xFF is the correct value for 0x5A and 0x5B. signaltap image (http://www.fps-tech.net/images/st.jpg) The code I am using to generate this is: /* Reset */ IOWR_8DIRECT(0,0,0xF0); /* Put into CFI Mode */ IOWR_8DIRECT(0,0xaa,0x98); /* Read IDs */ printf("0x%X 0x%X 0x%X 0x%X\n",IORD_8DIRECT(0,0x5a),IORD_8DIRECT(0,0x5b),IORD_8DIRECT(0,0x5c),IORD_8DIREC T(0,0x5d)); printf("0x%X 0x%X 0x%X 0x%X\n",IORD_8DIRECT(0,0x5e),IORD_8DIRECT(0,0x5f),IORD_8DIRECT(0,0x60),IORD_8DIREC T(0,0x61)); The base address is 0x0 for the Flash...