Honored ContributorHello,
I'd like to implement a dual port ram using on chip memory, with one side connected to the Avalon bus and other connected to an external DSP. Not sure where to get started; I can not seem to find a way to expose a DPRAM interface to external pins. Any suggestions as to where I can look? Thank you.
Honored ContributorHonored ContributorYou have to use a single clock and then enable OLD_DATA.
And still not do two writes to the same location. Note that feeding the same clock to both clock inputs doesn't count - the M9K has to be configured with a single clock input. If the Nios cpu (or other avalon master) is using a different clock then a clock crossing bridge will be added. I mostly know about this because we had issues with the sopc builder silently ignoring OLD_DATA for M9K dual ported between the avalon bus and tightly coupled memory. IMHO internal memory should always be tightly coupled to the nios cpu (unless you need the 2nd port for something else).Honored ContributorHonored ContributorHow does this scheme change if you instantiate a dpram outside of qsys, but wish to access it from nios (instruction and data)? The megafunction dp ram has just a few signals for each port (address, output read data, input write data, write enable, and clock), but the memory controllers in qsys are all s/dram based, with ras, cas, etc...
Incidentally, one of the reasons I'm looking at instantiating the memory OUTSIDE of qsys, is because quartus seems to have trouble fitting the design when I specify too large of a memory block in qsys. Interestingly, 15k won't fit, but 14k will.. and the fit summary shows only 25% memory utilization (and 65% logic)! So obviously, the 1k isn't causing it to run out of memory, it must be something else. Outside of qsys I can instantiate a 17k dpram (or much bigger) and it synthesizes fine, thus I'd like the nios to execute from this "external" memory.Honored ContributorI don't think the scheme changes at all; it is the same basic concept just applied slightly differently.
e.g. insert an Avalon-MM Pipeline Bridge, connect it's slave port to your NIOS, and export it's Master port as a conduit. In your toplevel, connect the master conduit pins to your dual port RAM.Honored ContributorThe 'memory utilisation' of 25% means that you are using 25% of the memory bits, not 25% of the memory blocks.
If something is using a small number of address or data bits in a memory block then the utilisation will be reported as low even though the other bits can't be used.Honored ContributorHonored ContributorReads happen every clock without an explicit enable (other than clken).
clken stops the address being latched so has the effect of holding the previous data-out even though the address is no longer present.Honored ContributorThank you. 1) Is clken active high? 2) Is chipselect active high? 3) Is reset for the onchip mem s2 active low?
Honored ContributorI just answered 3) in my last post false so reset is active high as are clken and chipselect.
