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Ok - if you need dual clock then you have to live with random data during concurrent read/write of the same address - note the you can get some bits of the old data and some of the new.
M9K don't have a 'read' signal, they do reads every cycle. You can use the clken to stop this - and keep the output data constant even though the address has changed.
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OK, thank You for the answer about Read.
What then could be the solution to have a real dual-port memory ( without the problems during concurrent read/write of the same address ) with one port being controlled by NIOS II and the other by custom logic?
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