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Yes, its correct!
Did You manage to connect External DSP to the exported second (s1) port of the dual port RAM?
If Yes , the please answer:
1). why Write signal is present, but the Read signal is missing on the exported second (s1) port of the dual port RAM?
2). Is Write really is WriteEnable?
3). how to use clken ( clock enable ) on the exported second (s1) port of the dual port RAM?
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Did you get an answer to this? I have the same question. Since there is no read signal exported the write must be a write/read_n or write high read low level? Is clken or chipselect used as a data strobe? Are all signals active high? clken, chipselect, write? byteenable is active high so if you specify byteenable as all ones 4'b1111 for 4 byte 32 bit interface you are writing all 32 bits in one write cycle.
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