Nios II with on-chip Dual port ram between Nios and External DSP

How does this scheme change if you instantiate a dpram outside of qsys, but wish to access it from nios (instruction and data)? The megafunction dp ram has just a few signals for each port (address, output read data, input write data, write enable, and clock), but the memory controllers in qsys are all s/dram based, with ras, cas, etc...

Incidentally, one of the reasons I'm looking at instantiating the memory OUTSIDE of qsys, is because quartus seems to have trouble fitting the design when I specify too large of a memory block in qsys. Interestingly, 15k won't fit, but 14k will.. and the fit summary shows only 25% memory utilization (and 65% logic)! So obviously, the 1k isn't causing it to run out of memory, it must be something else.

Outside of qsys I can instantiate a 17k dpram (or much bigger) and it synthesizes fine, thus I'd like the nios to execute from this "external" memory.