Nios II with on-chip Dual port ram between Nios and External DSP

What you probably want to do is create a Qsys component with an Avalon-MM Master, and conduit signals to connect to the DSP pins.

Here's one similar thread:

http://www.alteraforum.com/forum/showthread.php?t=3866

Thank you for your prompt response.

I will try what you've suggested. Just for clarification (please correct me if I am wrong):

1) I can create a dual port RAM component using Qsys; this DPRAM component will have two Avalon slave interfaces, s0, and s1.

2) The first slave interface s0 will connect to the master port of the Nios II processor via the Avalon fabric, and the second slave port s1 will connect to the Avalon-MM master component as you've suggested.

3) The newly created Avalon-MM component should be a 'dummy' that brings all of the master signals out via conduits? Then I can connect these to glue logic / pins as needed?

I see that the dual port memory has an option for two clock inputs; I assume I need to use this since the external interface will be in a different clock domain (ie the external memory interface)?

Best regards,

Scott

You are mostly correct, except how "dummy" your module is depends on how (dis)similar your DSP memory controller is when compared to Avalon-MM.

If you want to skip creating the Qsys component, you can simply "export" the second (s1) port of the dual port RAM.

When you do that, in your top level module you will get a series of signals like this:

    unsaved u0 (
        .onchip_memory2_0_s2_address    (<connected-to-onchip_memory2_0_s2_address>),    //     onchip_memory2_0_s2.address
        .onchip_memory2_0_s2_chipselect (<connected-to-onchip_memory2_0_s2_chipselect>), //                        .chipselect
        .onchip_memory2_0_s2_clken      (<connected-to-onchip_memory2_0_s2_clken>),      //                        .clken
        .onchip_memory2_0_s2_readdata   (<connected-to-onchip_memory2_0_s2_readdata>),   //                        .readdata
        .onchip_memory2_0_s2_write      (<connected-to-onchip_memory2_0_s2_write>),      //                        .write
        .onchip_memory2_0_s2_writedata  (<connected-to-onchip_memory2_0_s2_writedata>),  //                        .writedata
        .onchip_memory2_0_s2_byteenable (<connected-to-onchip_memory2_0_s2_byteenable>), //                        .byteenable
        .onchip_memory2_0_clk2_clk      (<connected-to-onchip_memory2_0_clk2_clk>),      //   onchip_memory2_0_clk2.clk
        .onchip_memory2_0_reset2_reset  (<connected-to-onchip_memory2_0_reset2_reset>)   // onchip_memory2_0_reset2.reset
    );

which maybe is close enough for your system.

Hello,

Thanks again, I was able to export the signals as suggested.

I have a question regarding the second clock on the DPRAM; can this clock be asynchronous with the first clock that is connected to the Nios system clock?

Best regards,

Scott

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I have a question regarding the second clock on the DPRAM; can this clock be asynchronous with the first clock that is connected to the Nios system clock?

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Yes. The two ports are independent.

If the clocks are different you'll get 'random' data if a read and write to the same location happen 'at the same time' (probably with any overlap between the two clock cycles).

You'll need to ensure that this doesn't happen, or that the read values don't matter.

Hello,

I've attached a screen shot showing the Qsys configuration and schematic; if possible, can you perhaps confirm if what I have shown is what was suggested?

Thank you and best regards,

Scott

--- Quote Start ---

Hello,

I've attached a screen shot showing the Qsys configuration and schematic; if possible, can you perhaps confirm if what I have shown is what was suggested?

Thank you and best regards,

Scott

--- Quote End ---

Yes, its correct!

Did You manage to connect External DSP to the exported second (s1) port of the dual port RAM?

If Yes , the please answer:

1). why Write signal is present, but the Read signal is missing on the exported second (s1) port of the dual port RAM?

2). Is Write really is WriteEnable?

3). how to use clken ( clock enable ) on the exported second (s1) port of the dual port RAM?

You can't use clken in dual port mode with a single clock (and you must use single clock mode to get OLD_DATA - which you probably want).

There is an alternate address hold (I think) signal which has basiaclly the same effect.

Ok - if you need dual clock then you have to live with random data during concurrent read/write of the same address - note the you can get some bits of the old data and some of the new.

M9K don't have a 'read' signal, they do reads every cycle. You can use the clken to stop this - and keep the output data constant even though the address has changed.