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Altera_Forum
Honored Contributor
12 years agoThank you for your prompt response.
I will try what you've suggested. Just for clarification (please correct me if I am wrong): 1) I can create a dual port RAM component using Qsys; this DPRAM component will have two Avalon slave interfaces, s0, and s1. 2) The first slave interface s0 will connect to the master port of the Nios II processor via the Avalon fabric, and the second slave port s1 will connect to the Avalon-MM master component as you've suggested. 3) The newly created Avalon-MM component should be a 'dummy' that brings all of the master signals out via conduits? Then I can connect these to glue logic / pins as needed? I see that the dual port memory has an option for two clock inputs; I assume I need to use this since the external interface will be in a different clock domain (ie the external memory interface)? Best regards, Scott