Gigabit Ethernet Interface (via Marvell 88E1111) with Cyclone IVE FPGA

Hi Daixiwen,

I increased the frame length from 62 to 1480 and Speed I am getting is 760 Mbps, quite good! (Which shows in the networking of Task Manager of my PC). But this frame is raw and yet to add IP Header and UDP Header to the frame by modifying the C program code.

I am wondering how I can modify this C program (available in previous attachment) to achieve this.

I am also wondering if this speed (760 Mbps) drops too much after adding IP Header and UDP Header. I think may be little but not too much. Isn't it?

one more thing, if I integrate this ethernet port with FPGA (Lets say giving input to ethernet port from FPGA after doing some processing on A/D converter output), will it still be compatible? I mean it doesn't affect in the current speed?

Oh yes I didn't notice in your code that you used the DMA driver directly and wasn't using a TCP/IP stack at all.

Indeed if you want to generate a correct UDP packet you will need to add the headers.

I suggest to change the length "0x00,0x2E" to an IP EtherType ("0x08, 0x00") so that you don't have to worry about the frame size and your packet is recognized as an IP packet.

Then instead of just the payload, you will need to put 20 bytes for the IP header and 4 or 8 more bytes for the UDP header. You can find the header definitions on Wikipedia:

https://en.wikipedia.org/wiki/internet_protocol_version_4#packet_structure https://en.wikipedia.org/wiki/user_datagram_protocol#packet_structure

Hi,

The ethernet transmit frame after changing the original code to ether type IP is:

unsigned char tx_frame[1024] = {

0x00,0x00, // for 32-bit alignment

0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, // destination address (broadcast)

0x01,0x60,0x6E,0x11,0x02,0x0F, // source address

0x08,0x00, // length or type of the payload data

'\0' // payload data (ended with termination character)

};

According to some internet source:

// The packet length# define PCKT_LEN 1024

// The IP header's structure

struct ipheader {

unsigned char iph_ihl:5, iph_ver:4;

unsigned char iph_tos;

unsigned short int iph_len;

unsigned short int iph_ident;

unsigned char iph_flag;

unsigned short int iph_offset;

unsigned char iph_ttl;

unsigned char iph_protocol;

unsigned short int iph_chksum;

unsigned int iph_sourceip;

unsigned int iph_destip;

};

// UDP header's structure

struct udpheader {

unsigned short int udph_srcport;

unsigned short int udph_destport;

unsigned short int udph_len;

unsigned short int udph_chksum;

};

// The checksum

unsigned short csum(unsigned short *buf, int nwords)

{ //

unsigned long sum;

for(sum=0; nwords>0; nwords--)

sum += *buf++;

sum = (sum >> 16) + (sum &0xffff);

sum += (sum >> 16);

return (unsigned short)(~sum);

}

char buffer[PCKT_LEN];

// Our own headers' structures

struct ipheader *ip;

struct udpheader *udp;

// Fabricate the IP header or we can use the

// standard header structures but assign our own values.

ip->iph_ihl = 5;

ip->iph_ver = 4;

ip->iph_tos = 16; // Low delay

ip->iph_len = sizeof(struct ipheader) + sizeof(struct udpheader);

//ip->iph_ident = htons(54321);

ip->iph_ident = 54321;

ip->iph_ttl = 64; // hops

ip->iph_protocol = 17; // UDP

// Source IP address, can use spoofed address here!!!

ip->iph_sourceip = 0xa074;

// The destination IP address

ip->iph_destip = 0xa073;

// Fabricate the UDP header. Source port number, redundant

udp->udph_srcport = 0x80;

// Destination port number

udp->udph_destport = 0x70;

udp->udph_len = sizeof(struct udpheader);

// Calculate the checksum for integrity

ip->iph_chksum = csum((unsigned short *)buffer, sizeof(struct ipheader) + sizeof(struct udpheader));

memcpy(buffer,&ip, sizeof(ip));

memcpy((buffer+ sizeof(ip)),&udp, sizeof(udp));

Now I am wondering how I can add this IP and UDP header to the raw data. I mean there is no any socket number or something like that. So where I have to map the variable buffer now?

Is it to change some parameters here(below) in original code? If yes, how? If not what is alternative?

// Create transmit sgdma descriptor

alt_avalon_sgdma_construct_mem_to_stream_desc( &tx_descriptor, &tx_descriptor_end, tx_frame, 1480, 0, 1, 1, 0 );

// Set up non-blocking transfer of sgdma transmit descriptor

alt_avalon_sgdma_do_async_transfer( sgdma_tx_dev, &tx_descriptor );

// Wait until transmit descriptor transfer is complete

while (alt_avalon_sgdma_check_descriptor_status(&tx_descriptor) != 0)

;

}

return 0;

}

Before filling up your IP and UDP header structures, you need to be sure that they point to the correct part of your buffer in tx_frame. ip should point to the area just after the Ethernet header that you already filled, and udp should point just after ip. Then your packet data should follow. Something like this:

( top level)
# define ETH_HEADER_SIZE 16 // 14 for the Ethernet header, + 2 for the 32-bit alignment packing bytes
( in your function, just after the struct ipheader *ip; and struct udpheader *udp; lines)
ip = (struct ipheader*)(tx_frame + ETH_HEADER_SIZE);
udp = (struct udpheader*)(tx_frame + ETH_HEADER_SIZE + sizeof(struct ipheader));

and write your data starting at tx_frame + ETH_HEADER_SIZE + sizeof(struct ipheader) + sizeof(struct udpheader)

You can set the destination port number in the udpheader structure (udph_destport)

Hi Daixiwen,

Here I just want to add IP and UDP header on the Raw Ethernet frame. The Ethernet is working at 760 Mbps with Raw data.

I edited the code as you suggested but not getting the desired result.

Could you please have a look on the code (attachment) to find where is the mistake?

Hi,

I need one information.

There are two ways to program FPGA for Hardware:

1. JTAG (Temporary)

2. Active Serial (Permanent)

In this ethernet case, If I run some application program written in C language (Software) using NIOS ii Eclipse on this generated hardware, How I can load this application software program on FPGA permanently?

This is clear to me that:

1. For Hardware programming: Choose Active Serial

2. But for Software: ???? I mean as long as I am connected to the FPGA board with NIOSII Eclipse via USB Blaster, it works but when I quit NIOSII Eclipse, it will no works anymore. Is there anyway to load also this application program software to the FPGA permanently alongside the Hardware. So that both Hardware and software work independently on the FPGA board regardless of whether they are connected to Quartus II and NIOS ii Eclipse or not.

I am sorry if my question is so obvious.

If the EPCS is the only flash you have on the board, you can boot from it if you have enough space left in it.

http://www.altera.com/literature/an/an458.pdf

Hi,

I am following the tutorial "using Triple speed Ethernet" and programmable file it generated is ...._time_limited.sof. I am able to run it on the board via JTAG. Now, I wanted to flash the board in Active serial mode and getting following popup window:

some devices in current device list cannot be added to selected programming mode active serial programming? do you want to clear all devices in current device list and switch to selected mode.

Beside this, there is also no .pof file generated to flash the board in active serial mode.

I know this is some kind of licence limitation.

I would like to flash the board with Hardware configuration file(.pof) and run application software program(C file) on it in active serial mode (standalone mode) to fulfill complete Gigabit Ethernet Implementation.

My question is:

Which licence is exactly needed and how much approximately does it cost?

When you compile the project, in the report go to Analysis & Synthesis > IP Cores Summary, and you will see a list of all the licensed IPs. That way you can see which ones you need.

You'll probably need at least the TSE core for Ethernet, the Nios CPU if you aren't using the /e version, and maybe a memory controller.

For the prices you should contact your local distributor for a proposal. In some cases they have packages with licenses for several IPs at a reduced price.