Honored ContributorHello,
I have a customboard design that uses the Cyclone EP1C20F324C7 device. Before I created my circuit board I created my design and let Quartus assign the pins, and I was able to achive an FMAX of 80MHZ (this was my goal) The problem is, when I locked in the pins that Quartus assigned in the Assignment editor, my FMAX decreases to about 68Mhz. Any help would be greatly appreciated! Brandon
Honored ContributorWell, this is part ofthe board design/fpga project iteration process. By letting Quartus do the assignment, you are letting it pick the most ideal spots. when you locked in your pins during board design, you obviously picked non-ideal locations, probably trading off with routability. There's not much you can do other than turning on fitter settings to the max so that it optimizes as much as possible.
It's a good lesson to learn though, I did the same thing.. whenever I put out boards now, I don't lock down pins until I run it through a Quartus compile to see the results. JHonored ContributorI guess that I was not very clear, I did let Quartus assign all the pins, and then in the assignment editor, I took the pins Quartus assigned and made those assignments, I then compiled again and got the results discussed above. The compilation was done with no change to the project. I was going to make a minor change however, I did not.
I was just wondering if using Logic Lock or one of the features that Quartus has, that I am unfamiliar with, would keep that original compilation and routing that was able to acheive the 80 MHZ. I do need to make a few minor changes to the project, and keep my FMAX close to 80 MHZ. Any ideas would be greatly appreciated. Maybe I am asking for too much! Thank-you for you help!! BrandonHonored ContributorHi BT,
Oh, Don't get me going about Fmax (see July 10th). Just a piece of simple advice given to me by my FAE which works (for me). In the Analysis and Syntheses settings, setting the Optimizaion Technique to 'balanced' usually produces a better Fmax than 'speed'. I guess it depends on how much of the Cyclone you are utilising though. Banx.Honored Contributor<div class='quotetop'>QUOTE </div>
--- Quote Start --- setting the Optimizaion Technique to 'balanced' usually produces a better Fmax than 'speed'.[/b] --- Quote End --- Just an anecdote: One time, when I ran DSE, it had 12 compilation points. The one that gave me the best Fmax had the optimization set for size (as well as routing effort=3 and placement effort=3)! As for the original question, why did locking the pins have an adverse effect on fmax, I have no idea. I guess I go about it in a completely different way. I place the pins so that the board layout is easy, and then keep synthesizing until timing is met. One other note: I have tried logic-lock several times, and never gotten good results. But that was before 6.0, so maybe it has improved.Honored ContributorI have done extensive research and testing on using Logic Lock with projects using SOPC Buidler and NIOS - through several discussions with my FAE and Altera, it was easily concluded that Logiclock is not centered around NIOS-based designs. FPGAs are traditionally used for non-processor type approaches, using custom logic, and this is where logic lock comes in handy. When using NIOS and the avalon fabric, you have little to no control/understanding of hwo the system is put together; you click a few buttons and it's done for you. In order to get logiclock working properly, you have to really understand the architecture of the RTL; which can only come with custom RTL, not Alteras RTL.
Perhaps they will improve it, but I have actually gone back to SDRAM from DDR now because of the minimum fmax required by DDR (~75M). Once you get a complex enough system, holding this frequency is really hard, and my compile times get ridiculously long. JHonored ContributorI appreciate all of your comments! I will give some of the suggestions a try and see what happens.
To me it seems odd that if you let Quartus assign all the pins, and you get a good FMAX, you should be able to lock them down and still achive the same FMAX. Thanks again for all your help!!! BrandonHonored ContributorAnother note on changing the synthesis optimization technique.
Here are the results from two runs that were identical other than the synthesis optimization technique: Balanced: Failed on 17 paths, worst slack -0.268 ns, compile time: 2:40 I didn't try optimizing for "size" but, at 2.5 hours a run, I don't have a lot of time to experiment. I think I'll stick with speed. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gifHonored ContributorI think I'll try another DSE run with just a seed swap and see if that can get me there.
Honored ContributorWouldn't it be great if you could tell Quartus to keep trying until it reaches the required Fmax. We could then just let it run overnight.
Banx.Honored Contributor
banx.
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--- Quote End --- You're in luck... That's what DSE does (basically)! If you have never tried DSE, in Quartus II go to Tools -> Launch Design Space Explorer. Then, once it opens you can go to Options -> Stop flow when 0 failing paths are achieved Select several seeds, select how hard you want it to try, then let it run... and run... and run...
