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Altera_Forum
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20 years ago

FMAX Problem

Hello, I have a customboard design that uses the Cyclone EP1C20F324C7 device. Before I created my circuit board I created my design and let Quartus assign the pins, and I was able to achive an...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

Another note on changing the synthesis optimization technique.

Here are the results from two runs that were identical other than the synthesis optimization technique:

Balanced: Failed on 17 paths, worst slack -0.268 ns, compile time: 2:40

I didn't try optimizing for "size" but, at 2.5 hours a run, I don't have a lot of time to experiment. I think I'll stick with speed.

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif