FMAX Problem

I have done extensive research and testing on using Logic Lock with projects using SOPC Buidler and NIOS - through several discussions with my FAE and Altera, it was easily concluded that Logiclock is not centered around NIOS-based designs. FPGAs are traditionally used for non-processor type approaches, using custom logic, and this is where logic lock comes in handy. When using NIOS and the avalon fabric, you have little to no control/understanding of hwo the system is put together; you click a few buttons and it's done for you. In order to get logiclock working properly, you have to really understand the architecture of the RTL; which can only come with custom RTL, not Alteras RTL.

Perhaps they will improve it, but I have actually gone back to SDRAM from DDR now because of the minimum fmax required by DDR (~75M). Once you get a complex enough system, holding this frequency is really hard, and my compile times get ridiculously long.

J