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Altera_Forum's avatar
Altera_Forum
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20 years ago

FMAX Problem

Hello, I have a customboard design that uses the Cyclone EP1C20F324C7 device. Before I created my circuit board I created my design and let Quartus assign the pins, and I was able to achive an...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

<div class='quotetop'>QUOTE </div>

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setting the Optimizaion Technique to &#39;balanced&#39; usually produces a better Fmax than &#39;speed&#39;.[/b]

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Just an anecdote: One time, when I ran DSE, it had 12 compilation points. The one that gave me the best Fmax had the optimization set for size (as well as routing effort=3 and placement effort=3)!

As for the original question, why did locking the pins have an adverse effect on fmax, I have no idea. I guess I go about it in a completely different way. I place the pins so that the board layout is easy, and then keep synthesizing until timing is met. One other note: I have tried logic-lock several times, and never gotten good results. But that was before 6.0, so maybe it has improved.