Honored Contributor
Honored ContributorWell, this is part ofthe board design/fpga project iteration process. By letting Quartus do the assignment, you are letting it pick the most ideal spots. when you locked in your pins during board design, you obviously picked non-ideal locations, probably trading off with routability. There's not much you can do other than turning on fitter settings to the max so that it optimizes as much as possible.
It's a good lesson to learn though, I did the same thing.. whenever I put out boards now, I don't lock down pins until I run it through a Quartus compile to see the results. J
