Configure NIOS firmware burning interface

@JitLoonL_Altera

Many thanks for your help!

I will try what I asked in Quartus and then ask you if I encounter more issues.

If it is possible to have a meeting at which I can share my desktop for you to guide me, it will great helpful and efficient.

@JitLoonL_Altera

I am still facing questions when I create a NIOS in Platform Designer. I am not using Quartus 18.1.

1) when I insert NIOS II, the JTAG IP is not automatically inserted.

2) if I add a JTAG IP manually, I cannot decide which JTAG pins should be exported.

Please see the following picture:

1) JTAG UART not inserted automatically

This is expected behavior in newer Quartus versions. The Nios II processor does not auto-insert the JTAG UART or the JTAG-to-Avalon bridge. You need to:

• Manually add the JTAG UART IP (for terminal I/O) or JTAG to Avalon Master Bridge (if needed for memory access during debug).

2) Exporting JTAG Pins

You do not export JTAG pins manually in Platform Designer — these are handled outside of Platform Designer in the top-level Quartus project.

So for clarification:

• jtag_uart_0 is not a physical JTAG interface — it's a virtual UART over the JTAG debug cable, so it doesn't need export.

• The real JTAG pins (TDI, TDO, TMS, TCK) are already handled by Quartus I/O assignments (you don’t add them in Platform Designer).

• You only export other peripheral interfaces (e.g., clk, reset, external memory), not JTAG pins.

Correct Setup Summary

To get NIOS II + JTAG UART working:

1. Add Nios II processor in Platform Designer.

2. Add JTAG UART IP manually.

3. Connect:

   • clk to system clock.

   • reset to system reset.

   • irq to Nios II's interrupt line (optional but recommended).

4. You do not need to export jtag_uart_0 — Quartus uses it automatically via USB Blaster.

5. After generating HDL, compile the project.

6. In Nios II SBT, you should see JTAG UART available for terminal connection.

I recommend referring to the following official Intel resources, which provide clear guidance on working with Platform Designer and Nios II systems. These documents should help clarify many of your questions and allow you to explore the design flow in more detail.

• Intel Quartus Prime Pro Edition User Guide: Platform Designer
  https://cdrdv2-public.intel.com/817606/ug-683609-817606.pdf

• Nios II Processor Reference Guide
  https://cdrdv2-public.intel.com/666887/n2cpu-nii5v1gen2-683836-666887.pdf

• Nios II Software Developer Handbook
  https://www.intel.com/programmable/technical-pdfs/683525.pdf

• Embedded Design Handbook
  https://www.intel.com/programmable/technical-pdfs/683689.pdf

Please go through these resources as they cover the fundamentals and should address most of the questions you've raised.

Dear@JitLoonL_Altera

I am now doing the following:
1) add NIOS II.

2) add UART which is used to communicate with outside MCU.

3) add SPI_ADC which is used to initialize ADC.

4) add SPI_Freq which is used to initialize frequency mixture.

5) add JTAG_UART which is used to program/burn bitstream(sof) and firmware(elf).

6) set NIOS vectors page as ROM.s1 and RAM.s1.

My questions are:

--> are my upper settings correct?

--> For JTAG, it is not added by Platform Designer automatically, but added by me manually. Did I add it correctly? how to export JTAG_UART's pins?

The generate nios_core interface is shown in the following picture from which we see that there is not JTAG pins exported.

Additional info.

When you don’t need to export JTAG pins:

• Standard Nios II and JTAG UART flow: If you are using the Nios II processor along with the JTAG UART IP (used for communication between the host and the processor), you don’t need to export physical JTAG pins.

• The JTAG interface (TCK/TDI/TDO/TMS) is already available and accessed directly through the FPGA’s built-in JTAG port, which is already on your development board.

• Toolchain like Quartus and the programmer tool automatically uses these JTAG ports without requiring you to manually export them.

Examples of when no export is needed:

• Using Nios II Debug Interface with JTAG UART in your Platform Designer.

• Working with the built-in JTAG interface for debugging and programming.

When you need to export JTAG pins:

• Custom or special JTAG interface: If you are designing a custom JTAG interface (for instance, creating your own soft JTAG in your IP), then you will need to manually export the JTAG-related pins.

• If your design requires a unique or non-standard JTAG setup (outside the typical Nios II + JTAG UART setup), this will require exporting the JTAG pins from Platform Designer.

Examples of when export is needed:

• Designing your own custom JTAG interface.

• Implementing a soft JTAG in your IP that requires dedicated pins for TDI, TDO, TMS, and TCK.

@JitLoonL_Altera

Thank you for you patient reply!

I still have 2 more questions about JTAG:

according to your explanation above, in FPGA, JTAG ports are automatically connected to FPGA hardware pins. what pins of FPGA are connected built-in JTAG ports?

The most detailed datasheet I can find is at: https://www.intel.com/content/www/us/en/docs/programmable/683251/current/document-revision-history-for-the-device.html

Do you have more detailed datasheet which tells me what FPGA pins are used for JTAG?

I set RAM == 122880B, and ROM==81920B.

The question is:

I cannot set RAM + ROM = 540KB which you told me in this thread.

Even if I slight reduce RAM + ROM which is slight smaller than 540KB, I still encounter the size too big issue.

@JitLoonL_Altera

Thank you for help!

I now can add NIOS and related interface in Platform Designer, and I am also able to build firmware in Eclipse successfully.

I get a new question:
I would like add a new GPIO to NIOS so that I can control the GPIO in C code to light the LED that is connected to FPGA pin. how to add GPIO to NIOS in Platform Designer? how to control the GPIO in C code? how to access those interface in C code? is there any example C code for reference?

@JitLoonL_Altera

I get new questions about burning ROM or flash.

in my Cyclone 10 FPGA, I instance NIOS II, RAM(120KB), ROM(80KB), UART, JTAG, but no EPCS Flash controller as which is not supported by Cyclone 10 family.

I am able to program jic file via JTAG and the tool: Quartus-->Tools-->Programmer.

but I can't add elf file to Quartus-->Tools-->Programmer. elf type file is not supported by Programmer which supports 5 types(sof, pof, jam, jbc, ekp, jic).

Eclipse-->NIOS II -->Flash Programmer, I can't program elf as well, because:

1) The tools report error: Target is broken and needs to be reset, however, Quartus-->Tools-->Programmer is able connect and burn jic file to flash.

2) I don't know where the elf is burned through Flash Programmer?

is there any detailed guide that tells me how to burn elf file to ROM that I instance in FPGA?

Hi @ZhiqiangLiang,

I believe that your doubts should have been answered and you have also started a new post for the question. Hence with no further clarification on this thread, it will be transitioned to community support for further help on doubts in this thread.

If that is not the case, you can always login to ‘ https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you for the questions and as always pleasure having you here.

Best Wishes

BB