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Rainwang's avatar
Rainwang
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1 month ago

How to use SDRAM IP core on Agilex 3?

I am testing my project on Atum Nios V starter kit from terasic, which bases on Agilex 3 (A3CZ135BB18AE7S) and SDRAM(IS42VM32160G-6BLI). my purpose is, realize a Nios V system with RTOS and use the SDRAM as the program ram of the RTOS.

My question: Agilex 3 is supported only by the higher version such as quartus pro 25.3, and the SDRAM ip is supported by previous old version quartus. do you have any solution that i can reuse the avalon interface SDRAM IP core on Agilex 3?

thanks.

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13 Replies

  • AvinashTh_Altera's avatar
    AvinashTh_Altera
    Icon for New Contributor rankNew Contributor
    1 month ago

    Hello,

    Terasic has released, A Nios V processor-based design example demonstrating how to sequentially display bitmap image files from a Micro SD card on an HDMI monitor on github. This design includes SDRAM controller.  Here the example design path is (github.com/terasic/Atum-A3-Nano/tree/rel/25.1/picture_viewer_1080p) This example design is targeted for Terasic Atum Nios V starter kit. 

    Please refer this design and modify as per your design requirement utilizing Nios V and SDRAM controller.

    Please let me know if you have any further questions. 

    Thanks

    • Rainwang's avatar
      Rainwang
      Icon for Contributor rankContributor
      1 month ago

      got it. thank you for the support, i am using the example for further evaluation.

      • 3LionsCT's avatar
        3LionsCT
        Icon for Occasional Contributor rankOccasional Contributor
        1 month ago

        Terasic told me that the DE23-Lite board uses the same FPGA - SDRAM combination and there is an example there. I used it as a starting point for my Atum A3 board.

        Now if only they would show us how to use the ethernet port!