ZhiqiangLiang
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Re: NIOS connected to IRQ from FPGA but not PIO
@StefanG_Altera Thank you! I have already done the OR-combine in RTL code of my IP, and output only 1 wire interrupt from my IP. Currently, the problem is, the generate ID is still -1. please see the following picture. If I manually change IRQ to 4 and ID to 0, the C code could successfully enter the ISR in my c code. The weird thing is that I have to manually change the number after I click "generate BSP".Stream DMA
Hi, There is a FIFO in my RTL code which is converted to an IP in Platform Designer. I connect my IP to NIOS II in PD. The FIFO reading interface is axi_stream. Please see the following picture. I would like to add a DMA which can transfer data from the FIFO to NIOS RAM. is there a suitable DMA for my design? The DMA document is much less in here: https://www.intel.com/content/www/us/en/docs/programmable/683130/25-1/dma-controller-core.html.Re: how to set those parameters of clock crossing bridge?
@KennyTan_Altera Thank you! your explanation is very clear. Your comments; the bridge should be configured with the Nios side as the master clock domain and the IP side as the slave. In my designed, I tried to connect master and slave of Clock Bridge reversed, but it can be run correctly. so I got confused. how should I connect master and slave. solution 1: Clock Bridge master <---> NIOS and Clock Bridge slave <--> my IP. solution 2: Clock Bridge master <---> my IP and Clock Bridge slave <--> NIOS.Avalon-MM Clock Crossing Bridge parameters setting
Hi, My FPGA model is Cyclone 10 LP 10CL120YF484. on Platform Designer, NIOS frequency is 80MHz, and my IP is 160MHz. In NIOS C code, I would like to read/write registers of my IP. In my design, I would like to add a Avalon-MM Clock Crossing Bridge between NIOS and my IP. The questions are: 1) what do those parameters mean in Avalon-MM Clock Crossing Bridge setting? 2) in my design(NIOS 80MHz, IP 160MHz), how to set those parameters? 3) If no parameters can make my design work, what NIOS frequency should I set?how to set those parameters of clock crossing bridge?
Hi, My FPGA model is Cyclone 10 LP 10CL120YF484. on Platform Designer, NIOS frequency is 80MHz, and my IP is 160MHz. In NIOS C code, I would like to read/write registers of my IP. In my design, I would like to add a Avalon-MM Clock Crossing Bridge between NIOS and my IP. The questions are: 1) what do those parameters mean in Avalon-MM Clock Crossing Bridge setting? 2) in my design(NIOS 80MHz, IP 160MHz), how to set those parameters? If no parameters can make my design work, what NIOS frequency should I set?Re: qspi driver in NIOS bsp in Cyclone 10
@Archer_Altera 1) about the programming ELF question, I have asked many questions. please read previous post. For example, I have asked what those parameters means when I convert elf to hex file. I asked the question when I convert Programming Files to hex. 2) The issue I am facing when I debug the C code in eclipse is outwardly related with Eclipse, but it is inwardly related with the hex file and offset address when I generated hex file. in addition, I don't know which region you are in, so I wait for your reply and post new questions immediately. However, you usually answer the new posted questions on the second day. I don't know why the answer is so slow.
