Forum Discussion
Occasional ContributorStream DMA
Hi,
There is a FIFO in my RTL code which is converted to an IP in Platform Designer.
I connect my IP to NIOS II in PD.
The FIFO reading interface is axi_stream. Please see the following picture.
I would like to add a DMA which can transfer data from the FIFO to NIOS RAM.
is there a suitable DMA for my design?
The DMA document is much less in here: https://www.intel.com/content/www/us/en/docs/programmable/683130/25-1/dma-controller-core.html.
3 Replies
tehjingy_AlteraRegular Contributor
Hi
Sorry for the late response.
It is suggested to use the mSGDMA instead of the DMA.
Regards
Jingyang, Teh
- tehjingy_Altera
Hi
Do you have any follow up question on this case?
Regards
Jingyang, Teh
- tehjingy_Altera
Hi
As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Regards
Jingyang, Teh
