Honored ContributorHello,
I have a Altera Cyclone III Development Board and try to synchronize some Videostreams. They are delayed horizontal and vertical. Is it possible to synchronize them onboard without using external elements? GenLock seems not to work, because I don't have a VCXO onboard. Thank you
Honored ContributorYou can synchronize all four video streams, you need a frame buffer for each input. This can be done internally in the FPGA if there is enough embedded memory to buffer a frame of video for each stream.
If you need to genlock the output, you'll need external devices to generate your output timing.Honored ContributorHonored ContributorIt probably isn't the clipper, as it's a simple block with fixed delays through it.
Are your four video inputs to the FPGA synchronized to each other? If not, then the delays are at your source. The frame buffer should have horizontal and vertical control pulses for the input and output paths. The input H&V pulses should come from each input, and the output H&V pulses should be the same for all four outputs.Honored ContributorHonored ContributorCan you explain exactly what it is that you are trying to achieve?
What are the four video inputs? Four cameras? Something else? Are you gen-locking the cameras with a sync pulse out from the FPGA? If you are using cameras and went them to be synchronized then the FPGA needs to be the timing master and you need it to send out a gen-lock sync pulse to each camera, so that they all start exposing simultaneously and will also all be read out at the exact same rate (Frames per Second). Maybe you can upload some screen shots of the offsets you are talking about. --- Quote Start --- The inputs are the same at each CVI, I splitted the source signal out of the SOPC Builder. Input => SOPC System => Self Programmed Mixer => Output SOPC System: CVI - Clipper - FrameBuffer - Scaler - CVO CVI - Clipper - FrameBuffer - Scaler - CVO CVI - Clipper - FrameBuffer - Scaler - CVO I clipped different parts of the video and have scaled them up. If I clipp always the same parts of a videostream, I get only an offset of a few pixels, which I can compensate by a self written Verilog code. But when I clipp different parts, i get an offset of around ~50% of all lines --- Quote End ---Honored Contributorhttps://www.alteraforum.com/forum/attachment.php?attachmentid=6624
--- Quote Start --- Can you explain exactly what it is that you are trying to achieve? --- Quote End --- Hi gwall, I try to explain: The signal comes from my notebook. I have a picture in which are 9 other pictures, like the picture I have uploaded. (I think I never wrote about four streams, they are 9 ;) ) It comes in over the Bitec HSMC Digital Audio/Video Adapter via DVI. In Quartus II, I have the SOPC system with 9 clocked video inputs, every input becomes the picture as his input. The clippers, which comes next the CVIs, clipps each one part of the input picture, so that I have the 9 different pictures (yes, they are all different, just a little bit). Then I scale them up and out of the SOPC system, I mix them together to achieve a 3D picture. If all Clippers clipp just the picture at the left top, they are delayed just a few pixel. But if I clipp different parts of the picture, the output streams are delayed vertical. What I mean with "delayed vertical" is, that I can see the vertical blankings (after the mixer) of 8 of the pictures, just the first is not delayed (because I use his h_sync and v_sync to mix all together). Because of the mixing procedure, I need all nine h_syncs and v_syncs to be exactly the same. Thank you!Honored ContributorHi,
Assuming I understood this correctly, the issue you are having is that the outputs from the CVOs are not synchronized. The user guide has a few sections about generator lock and aligning the CVO output to an incoming start_of_frame signal. Is it something that can be used to fix your problem? Edit: As gwall pointed out, you will also have to tie the output clock and the output SOF signal to the input clock and the input SOF signal.Honored ContributorHonored ContributorI am not sure that you can use frame locking without clock locking. It is likely that your input and output clocks are physically different. Even if they have the same advertised clock rate they will drift apart and I am not sure how the CVO and your output will cope with that. I believe the output stream will be unstable.
You will not be able to tie the SOF signals with Nios. This is better done in the top-level HDL file. The SOF signals are exported by the Qsys/SOPCBuilder system. --- Quote Start --- Hi, i read at the ug_vip.pdf, that I need a VCXO to do GenLock (Clock Locking). But I think my Board (Altera Cyclone III Development Board) don't have a VCXO. But do you think its possible to use Frame Locking instead of Clock Locking? I looked this training video from altera: http://www.altera.com/customertraining/webex/implementing_video_systems/player.html And it seems that I only have to tie the input and output SOF signal, like you and gwall said before, to use Frame Locking. If I can do so, is it correct that this could do it in NiosII: while (1) { cvo_1(sof) = cvi_1(sof); cvo_2(sof) = cvi_1(sof); cvo_3(sof) = cvi_1(sof); ... } Thank you! --- Quote End ---Honored Contributor
module CVI0_dout_arbitrator (
// inputs:
CVI0_dout_data,
CVI0_dout_endofpacket,
CVI0_dout_startofpacket,
CVI0_dout_valid,
Clipper0_din_ready_from_sa,
clk,
reset_n,
// outputs:
CVI0_dout_ready,
CVI0_dout_reset
)
;
